1 引言

隨著半導體工藝的發展，片上系統SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" 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title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" 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title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC" title="SOC">SOC已成為當今一種主流技術。基于IP復用的SOC設計是通過用戶自定義邏輯(UDL)和連線將IP核整合為一個系統，提高了設計效率，加快了設計過程，縮短了產品上市時間。但是隨著設計規模的增大，集成密度的提高，IP引腳的增多，IP的植入深度加大必然使得測試驗證工作繁重。據統計，在SOC設計中，各種內核的測試驗證工作所用的時間占整個設計過程的60％～80％，SOC及IP核的測試驗證已成為SOC技術發展的瓶頸。如何在最短的時間內高效迅速地通過IP核驗證與測試．并把其集成在SOC中成為業界關注的焦點和研究領域急待突破與實現的方向。

基于IP核復用的SOC，其IP核類型和來源都不相同，即使已驗證好的IP核在集成時也不能確保不出差錯。IP核被集成到SOC后，其輸入輸出端口也嵌入到SOC，原本可測的端口失去了原有的可控性和可觀測性，變得不可測。

因此人們一直尋求有效的測試驗證技術。本文給出了基于內建自測試方法(BIST)，在設計編譯碼器IP核的同時，考慮其測試外殼設計，以期提高IP核可測性。

2 測試結構

所謂測試，就是在被測電路的輸入引腳施加相應的激勵信號，然后檢測輸出引腳的響應，并將檢測的輸出引腳的響應與期望引腳的響應進行比較以判斷電路是否存在故障的過程。

IP核測試的目的在于檢測IP核是否存在功能和時序錯誤，從而對IP核進行修改，提高產品的可靠性。一般采用訪問、隔離、控制的手段對IP核的輸入端施加激勵來得到響應與期望的響應進行比較。嵌入式IP核的測試結構如圖1所示。

測試激勵源為嵌入式IP核生成測試所需的激勵。響應分析器對所得到的響應進行分析，如果相同則表明沒有故障，不同則表明存在故障。測試訪問機制是 SOC傳送數據的一種手段，它將測試激勵傳送到IP核的輸入端口并將測試響應從IP核的輸出端口傳送到響應分析器。測試外殼是IP核同訪問機制及器件其他邏輯之間的接口；測試外殼以實現片上核與核之間的測試隔離，也可以為IP核提供了測試數據傳送通道。

3 內建自測試原理

內建自測試是可測性設計的一種重要方法。其基本思想是讓電路自己生成測試向量，而非通過外部施加測試向量，并且依靠自身判斷所得到的結果是否正確。內建自測試原理圖如圖2所示。

其中測試外殼(wrapper)在IP核的設計之中就予以考慮。通過測試外殼外部可以控制BIST和正常模式的切換。測試外殼內部多采用邊界掃描模塊、移位寄存器或多路訪問器等，它起到訪問、隔離、控制的作用，可提高IP核的可測性。然而加入測試外殼會使IP核的面積開銷增大，因此必須在IP核的可測性和面積之間進行權衡。

4 內建自測試的實現

可控性指驅動一個節點為邏輯狀態0或1的難易程度；可觀測性指從外部端口觀察內部節點故障的難易程度；可測性就是指在整個電路全部節點的可控性和可觀測性。很顯然，高可測性比較容易產生測試向量并且測試效果良好。

為了提高IP核的可測性，在IP核的設計中就考慮了設計特定電路方便測試。以BIST實現IP核的測試，一般具有如下優勢：簡化測試接口；改善測試質量；降低測試成本；提高測試可靠性。

基于BIST的編譯碼器IP核測試實現框圖如圖3所示。

　　通過測試外殼控制輸入/輸出寄存器將編譯碼器隔離使它們互不影響，正常狀態和測試狀態能夠切換，提高了IP核的可測性。具體的實現過程如下：

(1)正常狀態下原始碼輸入編碼器，由其輸出的碼再進入譯碼器又轉換為原始碼；

(2)測試狀態下測試外殼的測試向量輸入編碼器，由其輸出的碼直接進入譯碼器，由譯碼器輸出的碼為測試響應輸出，使其與期望值比較；圖3中的模式選擇模塊的邏輯結構如圖4所示。


圖4中mod為模式選擇控制端，置0為正常狀態。當rood為1時，out_sel輸入測試向量，再由in_tem輸出，進入in_sel；當mod 為0時，cod_out輸出片外，從而實現了正常狀態和測試狀態的切換。可以用硬件描述語言編寫此邏輯電路。用VHDL描述如下：

此模式選擇模塊實現狀態之間的切換，電路簡單，易于實現。

5 結束語

BIST為嵌入式內核的測試提供了一個可解決的方案，其測試效果明顯，故障覆蓋率較高，實現簡單。通過加入測試外殼可以實現對IP核的訪問、隔離、控制，有效地提高了IP核的可測性。但是采用BIST會使電路面積增加額外開銷，必須在IP核的可測性和面積之間進行權衡。