中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.234711
中文引用格式： 文永森，羅曦，杜映洪，等. 基于晶圓級技術的PBGA電路設計與驗證[J]. 電子技術應用，2024，50(7)：55-58.
英文引用格式： Wen Yongsen，Luo Xi，Du Yinghong，et al. Design of PBGA circuit based on wafer level packaging technology[J]. Application of Electronic Technique，2024，50(7)：55-58.

Design of PBGA circuit based on wafer level packaging technology

Abstract： Wafer level packaging technology can achieve multi-chip interconnection. However, issues such as packaging size, number of layers, and packaging yield have limited its development in the process of circuit miniaturization. This article takes a fan out wafer level packaging circuit as an example. Based on advanced packaging technology, using software design and simulation optimization methods, combined with packaging experience and practical application scenarios, the organic substrate packaging design and manufacturing were completed through rewiring and chip flip chip interconnection, achieving the goal of low-cost and mass production of the circuit. The design concept and manufacturing process of this product can provide reference for the miniaturization development of other hardware circuits.

Key words : wafer level packaging；circuit miniaturization；chip flip chip；substrate packaging