中圖分類號(hào)：TN709 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234033
中文引用格式： 陳旻琦，鄧嵐清，楊琳韻. 基于FPGA的高速模數(shù)轉(zhuǎn)換器評(píng)估系統(tǒng)[J]. 電子技術(shù)應(yīng)用，2024，50(2)：96-101.
英文引用格式： Chen Minqi，Deng Lanqing，Yang Linyun. Evaluation system of high-speed anolog to digital converter based on FPGA[J]. Application of Electronic Technique，2024，50(2)：96-101.

Evaluation system of high-speed anolog to digital converter based on FPGA

Abstract： A　high speed anolog to digital converter (ADC) evaluation system based on field programmable logic array (FPGA) is designed and implemented. The logic codes are designed based on the FPGA, and the signal sampling and data transmission of ADC are controlled according to different test modes. The analog input signal is converted into digital data stored in the FPGA block RAMs, and transmitted through the user datagram protocol (UDP) to the upper computer designed in MATLAB, which processes the calculated data and output the test results to user. The parameters of a 16-bit ADC with a sampling rate of 100 MS/s are calculated and analyzed in the system. Experimental results show that this system can achieve high speed and high precision ADCs testing and evaluation.

Key words : FPGA；ADC；upper computer；MATLAB；Ethernet