中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.239807
中文引用格式： 姜姝，楊超，吳馳. 基于PG網(wǎng)絡的全流程優(yōu)化在高性能CPU內(nèi)核中的應用[J]. 電子技術應用，2023，49(8)：36-41.
英文引用格式： Jiang Shu，Yang Chao，Wu Chi. Application of fully automated optimization based on PG network in high performance CPU core[J]. Application of Electronic Technique，2023，49(8)：36-41.

Application of fully automated optimization based on PG network in high performance CPU core

Abstract： With the continuous improvement of the integration of high-performance computing chips and the advancement of technology, the width of metal wires is getting narrower and narrower, and the voltage drop (IR drop) will occur on the power network when the resistance on the chip power network increases and the high-density logic gate unit has a logic flip action at the same time, resulting in timing problems in the chip, and even the functional failure of the logic gate may occur. Based on the flash PG flow of the Cadence implementation tool Innovus, this paper completes the comprehensive implementation and rapid iteration of the PG network, and uses auto reinforce PG and trim PG to realize the trade-off between the voltage drop and timing of the high-performance CPU core from two aspects, and completes the whole process optimization of the PG network from floorplan to PR (Placement and Route) stage. The results show that under the premise of the same machine resources, flash PG flow can increase the speed of powerplan up to 10 times the original, especially in the design of the top level, which can effectively save the exploration time of PG mesh in the early stage of design. Auto reinforce PG and trim PG repair 66% of the dynamic IR drop violations by reinforcing the PG of the weak IR area and trimming the redundant PG respectively, and at the same time provide more winding resources for the design to achieve the purpose of not deteriorating the timing and DRC (Design Rule Check).

Key words : chip design；flasg PG；IR drop fixing