中圖分類(lèi)號(hào)：TN92
文獻(xiàn)標(biāo)志碼：A
DOI: 10.16157/j.issn.0258-7998.223229
中文引用格式： 黃沛昱，高磊，宋佳波. 基于自動(dòng)編譯碼器的端到端無(wú)線(xiàn)通信系統(tǒng)FPGA實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用，2023，49(5)：105-110.
英文引用格式： Huang Peiyu，Gao Lei，Song Jiabo. FPGA implementation of end-to-end wireless communication system based on auto-encoder[J]. Application of Electronic Technique，2023，49(5)：105-110.

FPGA implementation of end-to-end wireless communication system based on auto-encoder

Abstract： The communication system based on auto-encoder is a hot research field of communication system in recent years, and how to apply the end-to-end learning communication systems to embedded devices is a hot topic worthy of research. This paper proposes a FPGA design scheme for end-to-end wireless communication system based on auto-encoder, deploys the end-to-end wireless communication system based on auto-encoder on the FPGA, and uses the AD9361 radio frequency chip as the radio frequency front-end processing module to achieve real air transmission. In addition, a hardware acceleration scheme is designed for the CNN in the system, parallelism is explored in the convolution computing unit, and a pipeline architecture is designed to accelerate the convolution operation. For the storage unit, the double buffer design is adopted, and the ping-pong operation is used to improve the utilization rate of data communication bandwidth. The experimental results show that under different modulation methods, the BLER performance is close to the simulation results under the Rayleigh fading channel. Compared with the general-purpose CPU i5-9300, the network inference speed of the designed system is 3.98 times higher than that of the general-purpose CPU i5-9300 with the same block error rate. Compared to the Nvidia 1650 GPU, the power is about 0.18 times higher.

Key words : FPGA；auto-encoder；end to end communication；pipeline；AD9361