基于Cadence 3D-IC平臺的2.5D封裝Interposer設(shè)計(jì)
2022年電子技術(shù)應(yīng)用第8期
張 成，李 晴，趙 佳
格芯半導(dǎo)體(上海)有限公司 中國研發(fā)中心(上海)，上海201204
摘要： 2.5D先進(jìn)封裝區(qū)別于普通2D封裝，主要在于多了一層Silicon Interposer(硅中介層)，它采用硅工藝，設(shè)計(jì)方法相比普通2D封裝更為復(fù)雜。而高帶寬存儲(High Bandwidth Memory，HBM)接口的互連又是Interposer設(shè)計(jì)中的主要挑戰(zhàn)，需要綜合考慮性能、可實(shí)現(xiàn)性等多種因素。介紹了基于Cadence 3D-IC平臺的Interposer設(shè)計(jì)方法，并結(jié)合HBM接口的自動布線腳本可以快速實(shí)現(xiàn)Interposer設(shè)計(jì)；同時(shí)通過仿真分析確定了基于格芯65 nm三層金屬硅工藝的HBM2e 3.2 Gb/s互連設(shè)計(jì)規(guī)則，權(quán)衡了性能和可實(shí)現(xiàn)性，又兼具成本優(yōu)勢。
中圖分類號： TN47
文獻(xiàn)標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.229803
中文引用格式： 張成，李晴，趙佳. 基于Cadence 3D-IC平臺的2.5D封裝Interposer設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2022，48(8)：46-50，59.
英文引用格式： Zhang Cheng，Li Qing，Zhao Jia. 2.5D packaging interposer design based on Cadence 3D-IC platform[J]. Application of Electronic Technique，2022，48(8)：46-50，59.
文獻(xiàn)標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.229803
中文引用格式： 張成，李晴，趙佳. 基于Cadence 3D-IC平臺的2.5D封裝Interposer設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2022，48(8)：46-50，59.
英文引用格式： Zhang Cheng，Li Qing，Zhao Jia. 2.5D packaging interposer design based on Cadence 3D-IC platform[J]. Application of Electronic Technique，2022，48(8)：46-50，59.
2.5D packaging interposer design based on Cadence 3D-IC platform
Zhang Cheng，Li Qing，Zhao Jia
China R & D Center，Globalfoundries China(Shanghai) Co. Limited，Shanghai 201204，China
Abstract： With the rise of industries such as big data, artificial intelligence and 5G, there is a huge demand for high-speed computation, high-speed interface and low-power chip solutions. Therefore, advanced packaging, which plays a significant role in the continuation of Moore′s Law, including 2.5D and 3D packaging technology, has become an important topic in the semiconductor industry. The main difference between the 2.5D advanced packaging and the traditional 2D packaging is that there is an extra layer of silicon interposer, which uses the thin metal line width and fine metal spacing capabilities of the silicon process to achieve high density interconnection. This article described a design flow implemented with Cadence 3D-IC platform by which a 2.5D packaging interposer design is developed on Globalfoundries 65nm technology process. HBM2e 3.2 Gb/s high speed interconnect on a 3-Metal-Interposer is achieved and verified by signal and power integrity simulation and analysis making this product has both performance and cost advantages.
Key words : 2.5D advanced package；Si-interposer；HBM；3D-IC
0 引言
隨著人工智能、5G、大數(shù)據(jù)、云計(jì)算等行業(yè)的興起，典型的帶有HBM接口的2.5D先進(jìn)封裝應(yīng)用也越來越普遍，隨之而來的是對這類先進(jìn)封裝的設(shè)計(jì)需求也日益旺盛。由于2.5D先進(jìn)封裝設(shè)計(jì)中的Interposer采用硅工藝，設(shè)計(jì)相對復(fù)雜，而且HBM接口速率的不斷提升，對Interposer的設(shè)計(jì)也提出了更高的挑戰(zhàn)。本文結(jié)合設(shè)計(jì)實(shí)例，介紹了基于Cadence 3D-IC平臺的Interposer設(shè)計(jì)過程，從前期分析、物理實(shí)現(xiàn)到HBM2e接口仿真驗(yàn)證。
本文詳細(xì)內(nèi)容請下載：http://www.jysgc.com/resource/share/2000004649。
作者信息：
張 成，李 晴，趙 佳
(格芯半導(dǎo)體(上海)有限公司 中國研發(fā)中心(上海)，上海201204)
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