中圖分類號(hào)： TN402 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.212288 中文引用格式： 林純熙，粟濤. Yolo神經(jīng)網(wǎng)絡(luò)在集成電路焊盤布局規(guī)則檢測上的應(yīng)用研究[J].電子技術(shù)應(yīng)用，2022，48(7)：40-43，48. 英文引用格式： Lin Chunxi，Su Tao. Rule check of pad placement in IC layout with Yolo[J]. Application of Electronic Technique，2022，48(7)：40-43，48.
Rule check of pad placement in IC layout with Yolo
Lin Chunxi1，Su Tao2
1.International College，Beijing University of Posts and Telecommunications，Beijing 100001，China； 2.School of Electronics and Information Engineering，Sun Yat-sen University，Guangzhou 510006，China
Abstract： The application of deep learning on electronic design automation of integrated circuits is an interesting topic. This paper investigates the possibility of using Yolo v3 neural network to perform layout checks, which uses the arrangement rules between power and ground pads as inspection cases. In order to generate a training picture set, we use a custom Python script to generate layout sample pictures in batches and utilize LabelImg to label. The Yolo v3 layout checker is written under the TensorFlow framework. Evaluations demonstrate that the proposed layout checker achieves both high accuracy and high recall rate when judging the correctness of the pad layout. Additionally, the inspector is further tested by adjusting the size, shape, symmetry, and number of pads of the layout. Under such circumstances, the inspector still possesses an outstanding performance, showing great scalability. Our research reveals that the Yolo v3 neural network is able to find out errors in pad layout efficiently. Deep learning has great potential in integrated circuit layout inspection, which is worthy of further exploration.
Key words : integrated circuits；electronic design automation；layout check；deep learning；neural network
