基于Palladium AVIP的SoC驗證方案
2021年電子技術應用第8期
程 濤
哲庫科技(上海)有限公司，上海201210
摘要： 由于片上系統芯片(System on Chip，SoC)規模越來越大，軟件仿真速度在一些大的場景測試用例下已經很難滿足驗證計劃時間的要求。現場可編程門陣列(Field Programmable Gate Array，FPGA)原型驗證平臺容量的限制，以及需要修改時鐘樹等特性導致FPGA平臺并不適合做功耗/性能評估。基于Emulator平臺的仿真加速以及功耗/性能評估已經成為一種趨勢。可以使用Emulator的加速驗證知識產權(Accelerated Verification Intellectual Property，AVIP)替換軟件仿真用的驗證知識產權(Verification Intellectual Property，VIP)來做仿真加速。以及使用高級微控制器總線結構(Advanced Micro-controller Bus Architecture，AMBA) AVIP來模擬或者監控總線的傳輸，結合其他工具可以用來做功能/功耗/性能相關的驗證工作，大大加速了芯片相關開發驗證的進程。
中圖分類號： TN402
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.219803
中文引用格式： 程濤. 基于Palladium AVIP的SoC驗證方案[J].電子技術應用，2021，47(8)：52-55.
英文引用格式： Cheng Tao. SoC verification solution based on Palladium AVIP[J]. Application of Electronic Technique，2021，47(8)：52-55.
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.219803
中文引用格式： 程濤. 基于Palladium AVIP的SoC驗證方案[J].電子技術應用，2021，47(8)：52-55.
英文引用格式： Cheng Tao. SoC verification solution based on Palladium AVIP[J]. Application of Electronic Technique，2021，47(8)：52-55.
SoC verification solution based on Palladium AVIP
Cheng Tao
ZEKU Technology(Shanghai) Co.，Ltd.，Shanghai 201210，China)
Abstract： Due to the increasing scale of the chip, the EDA simulation speed has been difficult to meet the schedule requirements in some large scene cases. At the same time, the capacity of the FPGA prototype verification platform is limited, and some clock trees need to be modified and are not suitable for power/performance evaluation. Simulation acceleration and power analysis and performance evaluation based on Emulator platform have become a trend. Based on the emulator AVIP to simulate or monitor related bus transaction can be used to do the related work of function/power/performance which can greatly accelerated the process of chip development. The test cases developed based on MIPI AVIP for verifying MIPI or using MIPI to verify the internal image processing module achieves dozens of times of acceleration ratio and greatly improves the simulation speed. As well as using AVIP to simulate and monitor the behavior of related modules，can get the netlist power data and performance data. It has made an important contribution to the functional verification and power/performance optimization of the chip.
Key words : Emulator；AVIP；simulation acceleration；power analysis；performance estimation
0 引言
本文主要聚焦于消費電子類的SoC芯片驗證領域，為芯片驗證過程中遇到的功能、功耗、性能驗證方面的一些難題提供了有效的解決方案。相比傳統的驗證方式，基于Palladium AVIP的驗證方案能更加快速高效地達成驗證目的，為芯片按時成功流片提供了強有力的保障。
本文詳細內容請下載:http://www.jysgc.com/resource/share/2000003699，
作者信息:
程 濤
(哲庫科技(上海)有限公司，上海201210)
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