中圖分類號： TN402 文獻(xiàn)標(biāo)識碼： A DOI：10.16157/j.issn.0258-7998.200011 中文引用格式： 李俊，任連新，廖振雄. 基于FPGA的自定義CPU架構(gòu)設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2020，46(5)：40-43，49. 英文引用格式： Li Jun，Ren Lianxin，Liao Zhenxiong. Design of custom CPU architecture based on FPGA[J]. Application of Electronic Technique，2020，46(5)：40-43，49.
Design of custom CPU architecture based on FPGA
Li Jun1，Ren Lianxin2，Liao Zhenxiong3
1.Shenzhen Co-trust Technology Limited Company，Shenzhen 518055，China； 2.College of Automation Science and Engineering，South China University of Technology，Guangzhou 510640，China； 3.Shenzhen Kechuangsi Technology Limited Company，Shenzhen 518055，China
Abstract： In order to meet the needs of more and more distributed computing in current industrial applications, this article proposes a way to build a custom instruction set CPU in an FPGA chip. In this way, the FPGA has the ability to process instructions similar to a microcontroller. Moreover, the premise of this capability is the reuse of computing units, so resource consumption is limited and will not increase as the amount of calculation increases. In the improved architecture of the custom instruction set CPU, a parallel computing structure is used, which greatly improves the operation speed. Finally, combining the actual application case, the FOC algorithm in the current loop calculation is transplanted to the operation in the custom CPU. And ModelSim software is used to simulate, its calculation time is only 7.48 μs.
Key words : custom instruction set；CPU architecture；FPGA；parallel computing structure；FOC
