</a>TMS320C6748" title="TMS320C6748">TMS320C6748" title="TMS320C6748">TMS320C6748數(shù)字信號處理器(DSP),主要用在醫(yī)療,工業(yè)設備,音頻設備以及通信產(chǎn)品.本文介紹了TI 公司的TMS320C6748定點/浮點數(shù)字信號處理器(DSP)主要特性,方框圖,以及Zoom™ OMAP-L138 EVM開發(fā)套件主要特性, 應用基板電路圖和材料清單, 用戶接口板電路圖和材料清單.
The device is a low-power applications processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.
The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.
For security enabled devices, TI’s Basic Secure Boot allows users to protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust”, the secure boot flow guarantees a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks but can be enabled during the secure boot process during application development. The boot modules themselves are encrypted while sitting in external non-volatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. This protects customers’ IP and enables them to securely set up the system and begin device operation with known, trusted code. Basic Secure Boot utilizes either SHA-1 or SHA-256, and AES-128 for boot image validation. It also uses AES-128 for boot image encryption. The secure boot flow employs a multi-layer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer creates a new encrypted image using its encryption keys. Then the device can acquire the image via an external interface, such as Ethernet, and overwrite the existing code.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output(GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.
The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).
The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on each of two channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters.
A Video Port Interface (VPIF) is included providing a flexible video input/output port. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The device has a complete set of development tools for the DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
TMS320C6748主要特性:
圖1.TMS320C6748功能方框圖
Zoom™ OMAP-L138 EVM 開發(fā)套件
Logic PD’s product-ready software and hardware platforms fast forward your product development while reducing risk and controlling costs. The Zoom OMAP-L138 EVM Development Kit is a high-performance application development kit for evaluating the functionality of Texas Instruments’ energy-efficient OMAP-L138 applications processor, TMS320C6748 Digital Signal Processor (DSP), and Logic PD’s System on Module (SOM).
Application development is performed right on the product-ready OMAP-L138 SOM-M1 and software Board Support Packages (BSPs) included in the kit, which enables you to seamlessly transfer your application code and hardware into production. The included SOMs provide easy evaluation of the OMAP-L138 processor and TMS320C6748 DSP.
The OMAP-L138 SOM-M1 is ideal for applications that require high-speed data transfer and high-capacity storage, such as test and measurement, public safety radios, audio applications, and intelligent occupancy sensors. The OMAP-L138 and TMS320C6748 offer a universal parallel port (uPP) and are the first TI devices with an integrated Serial Advanced Technology Attachment (SATA) interface. For medical, industrial, audio, and communication products, the OMAP-L138 SOM?M1 allows for powerful versatility, long-life, and greener products.
The Zoom OMAP-L138 EVM Development Kit includes two SOMs (OMAP-L138 SOM-M1 and C6748 SOM-M1), application baseboard, 4.3” WQVGA LCD panel, user interface (UI) board, accessories, and software required to immediately begin development work.
圖2.ZOOM OMAP-L138 EVM開發(fā)套件外形圖
圖3.ZOOM OMAP-L138 EVM開發(fā)套件應用基板外形圖
圖4.ZOOM OMAP-L138 EVM開發(fā)套件用戶接口板外形圖
Application Baseboard:
圖5.應用基板電路圖(1)
圖6.應用基板電路圖(2)
圖7.應用基板電路圖(3)
圖8.應用基板電路圖(4)
圖9.應用基板電路圖(5)
圖10.應用基板電路圖(6)
圖11.應用基板電路圖(7)
圖12.應用基板電路圖(8)
圖13.應用基板電路圖(9)
圖14.應用基板電路圖(10)
圖15.應用基板電路圖(11)
圖16.應用基板電路圖(12)
應用基板電材料清單:
圖17.用戶接口板電路圖(1)
圖18.用戶接口板電路圖(2)
圖19.用戶接口板電路圖(3)
圖20.用戶接口板電路圖(4)
圖21.用戶接口板電路圖(5)
圖22.用戶接口板電路圖(6)
圖23.用戶接口板電路圖(7)
圖24.用戶接口板電路圖(8)
圖25.用戶接口板電路圖(9)
圖26.用戶接口板電路圖(10)
圖27.用戶接口板電路圖(11)
圖28.用戶接口板電路圖(12)
圖29.用戶接口板電路圖(13)
用戶接口板材料清單:
詳情請見:
http://www.ti.com/lit/ds/symlink/tms320c6748.pdf
和
http://support.logicpd.com/downloads/1361/
The device is a low-power applications processor based on a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.
The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
Although the DSP L2 is accessible by other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.
For security enabled devices, TI’s Basic Secure Boot allows users to protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based “root-of-trust”, the secure boot flow guarantees a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks but can be enabled during the secure boot process during application development. The boot modules themselves are encrypted while sitting in external non-volatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. This protects customers’ IP and enables them to securely set up the system and begin device operation with known, trusted code. Basic Secure Boot utilizes either SHA-1 or SHA-256, and AES-128 for boot image validation. It also uses AES-128 for boot image encryption. The secure boot flow employs a multi-layer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect customer encryption keys. When an update is needed, the customer creates a new encrypted image using its encryption keys. Then the device can acquire the image via an external interface, such as Ethernet, and overwrite the existing code.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output(GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.
The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps).
The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on each of two channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters.
A Video Port Interface (VPIF) is included providing a flexible video input/output port. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The device has a complete set of development tools for the DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
TMS320C6748主要特性:
圖1.TMS320C6748功能方框圖
Zoom™ OMAP-L138 EVM 開發(fā)套件
Logic PD’s product-ready software and hardware platforms fast forward your product development while reducing risk and controlling costs. The Zoom OMAP-L138 EVM Development Kit is a high-performance application development kit for evaluating the functionality of Texas Instruments’ energy-efficient OMAP-L138 applications processor, TMS320C6748 Digital Signal Processor (DSP), and Logic PD’s System on Module (SOM).
Application development is performed right on the product-ready OMAP-L138 SOM-M1 and software Board Support Packages (BSPs) included in the kit, which enables you to seamlessly transfer your application code and hardware into production. The included SOMs provide easy evaluation of the OMAP-L138 processor and TMS320C6748 DSP.
The OMAP-L138 SOM-M1 is ideal for applications that require high-speed data transfer and high-capacity storage, such as test and measurement, public safety radios, audio applications, and intelligent occupancy sensors. The OMAP-L138 and TMS320C6748 offer a universal parallel port (uPP) and are the first TI devices with an integrated Serial Advanced Technology Attachment (SATA) interface. For medical, industrial, audio, and communication products, the OMAP-L138 SOM?M1 allows for powerful versatility, long-life, and greener products.
The Zoom OMAP-L138 EVM Development Kit includes two SOMs (OMAP-L138 SOM-M1 and C6748 SOM-M1), application baseboard, 4.3” WQVGA LCD panel, user interface (UI) board, accessories, and software required to immediately begin development work.
圖2.ZOOM OMAP-L138 EVM開發(fā)套件外形圖
圖3.ZOOM OMAP-L138 EVM開發(fā)套件應用基板外形圖
圖4.ZOOM OMAP-L138 EVM開發(fā)套件用戶接口板外形圖
Application Baseboard:
圖5.應用基板電路圖(1)
圖6.應用基板電路圖(2)
圖7.應用基板電路圖(3)
圖8.應用基板電路圖(4)
圖9.應用基板電路圖(5)
圖10.應用基板電路圖(6)
圖11.應用基板電路圖(7)
圖12.應用基板電路圖(8)
圖13.應用基板電路圖(9)
圖14.應用基板電路圖(10)
圖15.應用基板電路圖(11)
圖16.應用基板電路圖(12)
應用基板電材料清單:
圖17.用戶接口板電路圖(1)
圖18.用戶接口板電路圖(2)
圖19.用戶接口板電路圖(3)
圖20.用戶接口板電路圖(4)
圖21.用戶接口板電路圖(5)
圖22.用戶接口板電路圖(6)
圖23.用戶接口板電路圖(7)
圖24.用戶接口板電路圖(8)
圖25.用戶接口板電路圖(9)
圖26.用戶接口板電路圖(10)
圖27.用戶接口板電路圖(11)
圖28.用戶接口板電路圖(12)
圖29.用戶接口板電路圖(13)
用戶接口板材料清單:
詳情請見:
http://www.ti.com/lit/ds/symlink/tms320c6748.pdf
和
http://support.logicpd.com/downloads/1361/
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