Lattice公司的MachXO2系列是超低功耗的非易失PLD器件，容量從256到6864查找表（LUT），19個到 335個 I/O。此外，器件還集成了嵌入?yún)^(qū)塊RAM（EBR）（多達(dá)240Kb），分布式RAM(多達(dá)54kb)，用戶閃存（UFM）(多達(dá)3256kb)，PLL以及SPI，I2C和JTAG等接口。待機(jī)功耗低到19uW，主要用在低成本量大的消費類電子和系統(tǒng)應(yīng)用。本文介紹了MachXO2系列主要特性，方框圖以及MachXO2 Pico 開發(fā)板主要特性，方框圖，電路圖和材料清單（BOM）。
The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), pre-engineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications. The MachXO2 devices are designed on a 65nm non-volatile low power process. The device architecture has sev-eral features such as programmable low swing differential I/Os and the ability to turn off I/O banks, on-chip PLLs and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family. The MachXO2 devices are available in two versions – ultra low power (ZE) and high performance (HC and HE) devices. The ultra low power devices are offered in three speed grades -1, -2 and -3, with -3 being the fastest. Sim-ilarly, the high-performance devices are offered in three speed grades: -4, -5 and -6, with -6 being the fastest. HC devices have an internal linear voltage regulator which supports external VCC supply voltages of 3.3V or 2.5V. ZE and HE devices only accept 1.2V as the external VCC supply voltage. With the exception of power supply voltage all three types of devices (ZE, HC and HE) are functionally compatible and pin compatible with each other. The MachXO2 PLDs are available in a broad range of advanced halogen-free packages ranging from the space saving 2.5x2.5 mm WLCSP to the 23x23 mm fpBGA. MachXO2 devices support density migration within the same package. Table 1-1 shows the LUT densities, package and I/O options, along with other key parameters.
The pre-engineered source synchronous logic implemented in the MachXO2 device family supports a broad range of interface standards, including LPDDR, DDR, DDR2 and 7:1 gearing for display I/Os. The MachXO2 devices offer enhanced I/O features such as drive strength control, slew rate control, PCI compati-bility, bus-keeper latches, pull-up resistors, pull-down resistors, open drain outputs and hot socketing. Pull-up, pull-down and bus-keeper features are controllable on a “per-pin” basis. A user-programmable internal oscillator is included in MachXO2 devices. The clock output from this oscillator may be divided by the timer/counter for use as clock input in functions such as LED control, key-board scanner and sim-ilar state machines. The MachXO2 devices also provide flexible, reliable and secure configuration from on-chip Flash memory. These devices can also configure themselves from external SPI Flash or be configured by an external master through the JTAG test access port or through the I2C port. Additionally, MachXO2 devices support dual-boot capability (using external Flash memory) and remote field upgrade (TransFR) capability. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO2 device. These tools extract the timing from the routing and back-annotate it into the design for timing verification. Lattice provides many pre-engineered IP (Intellectual Property) LatticeCORE™ modules, including a number of reference designs licensed free of charge, optimized for the MachXO2 PLD family. By using these configurable soft core IP cores as standardized blocks, users are free to concentrate on the unique aspects of their design, increas-ing their productivity.
MachXO2系列主要特性：
Flexible Logic Architecture
• Six devices with 256 to 6864 LUT4s and ? 19 to 335 I/Os
Ultra Low Power Devices
• Advanced 65 nm low power process
• As low as 19 μW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
Embedded and Distributed Memory
• Up to 240 Kbits sysMEM™ Embedded Block RAM
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic
On-Chip User Flash Memory
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I2C and JTAG interfaces
• Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
• Programmable sysIO™ buffer supports wide range of interfaces:
–LVCMOS 3.3/2.5/1.8/1.5/1.2
–LVTTL
–PCI
–LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
–SSTL 25/18
–HSTL 18
–Schmitt trigger inputs, up to 0.5V hysteresis
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
Flexible On-Chip Clocking
• Eight primary clocks
• Up to two edge clocks for high-speed I/O ? interfaces (top and bottom sides only)
• Up to two analog PLLs per device with ? fractional-n frequency synthesis
Non-volatile, Infinitely Reconfigurable
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I2C
• Supports background programming of non-vola-tile memory
• Optional dual boot with external SPI memory
TransFR™ Reconfiguration
• In-field logic update while system operates
Enhanced System Level Support
• On-chip hardened functions: SPI, I2C, timer/ counter
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating range
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
Broad Range of Package Options
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA, fpBGA package options
• Small footprint package options
• Density migration supported
• Advanced halogen-free packaging
圖1。MachXO2-1200器件方框圖（頂視圖）
圖2。MachXO2-4000器件方框圖（頂視圖）
MachXO2 Pico 開發(fā)板
MachXO2 Pico 開發(fā)板主要特性：
The MachXO2 Pico Development Kit includes:
• MachXO2 Pico Evaluation Board
The MachXO2 Pico Evaluation Board features the following on-board com-ponents and circuits:
MachXO2 LCMXO2-1200ZE PLD device in a 132-ball csBGA package. The board is designed for density migration, allowing a lower density MachXO2 device to be assembled on the board.
4 Mbit SPI Flash memory
Current sensor circuits using Delta-Sigma ADC
LCD driven with PWM analog output circuitry
Expansion header for JTAG, SPI, I2C and PLD I/Os
4 capacitive touch sense buttons
Standard USB cable for device programming
RS-232/USB and JTAG/USB interface
RoHS-compliant packaging and process
USB or 2032 battery powered
• Pre-loaded Reference Designs and Demo
The kit includes a pre-loaded Pico SoC Demo design that inte-grates several Lattice reference designs including: the LatticeMico8 microcontroller, master WISHBONE bus controller, soft delta-sigma ADC, SPI master controller, UART peripheral, Embeded Block RAM and additional control functions.
• USB connector Cable
A mini B USB port provides power, a communication and debug port via a USB-to-RS- 232 physical channel and programming interface to the MachXO2 JTAG port.
• Battery
A 2032 coin battery can provides an alternate source of power.
• QuickSTART Guide
– Provides information on connecting the MachXO2 Pico Evaluation Board, installing Win-dows hardware drivers, and running the Pico SoC Demo.
圖3。MachXO2 Pico 開發(fā)板外形圖
圖4。Pico SoC演示方框圖
圖5。MachXO2 Pico 開發(fā)板電路圖（1）
圖6。MachXO2 Pico 開發(fā)板電路圖（2）
圖7。MachXO2 Pico 開發(fā)板電路圖（3）
圖8。MachXO2 Pico 開發(fā)板電路圖（4）
圖9。MachXO2 Pico 開發(fā)板電路圖（5）
圖10。MachXO2 Pico 開發(fā)板電路圖（6）
MachXO2 Pico 開發(fā)板材料清單（BOM）：
詳情請見：
http://www.latticesemi.com/documents/DS1035.pdf
和
http://www.latticesemi.com/documents/doc41110x86.pdf
以及
http://www.latticesemi.com/documents/doc41155x63.pdf
