中圖分類號(hào)：TN407 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.250807
中文引用格式： 徐加山，何金鑫，劉紅云，等. 探索分布式仿真方法加速Chiplet系統(tǒng)級(jí)驗(yàn)證[J]. 電子技術(shù)應(yīng)用，2025，51(8)：35-39.
英文引用格式： Xu Jiashan，He Jinxin，Liu Hongyun，et al. Research on accelerating chiplet system level verification with distributed simulation technology[J]. Application of Electronic Technique，2025，51(8)：35-39.

Research on accelerating chiplet system level verification with distributed simulation technology

Abstract： With the increasing demand for chip computing power in the fields of AI and high-performance computing, the chiplet solution is attracting more and more attention in the industry. However, the expansion of complexity and scale in multi-Die systems leads to issues such as high server resource consumption during simulation and extended verification delivery cycles. To solve these problems, this paper analyzes the traditional three-step method and socket verification method, and focuses on the Cadence distributed simulation solution. Based on an actual chiplet project, this paper breaks down system-level simulation tasks into multiple sub-Dies for parallel execution, and explores distributed simulation measures to improve efficiency from multiple aspects, such as server memory, cross-server communication delay, precise synchronization time adjustment, signal connection start time, and signal connection quantity. This achieves ultra-large-scale chiplet system-level RTL simulation and improves regression efficiency.

Key words : chiplet；system level validation；distributed simulation technology