中圖分類號：TP206
文獻標志碼：A
DOI: 10.16157/j.issn.0258-7998.223577
中文引用格式： 申曉敏，錢禮華，杜劍英，等. 基于USB2.0總線的NAND Flash檢測及控制方法[J]. 電子技術應用，2023，49(6)：44-48.
英文引用格式： Shen Xiaomin，Qian Lihua，Du Jianying，et al. NAND Flash detection and control method based on USB2.0 bus[J]. Application of Electronic Technique，2023，49(6)：44-48.

NAND Flash detection and control method based on USB2.0 bus

Abstract： At present, NAND Flash memory is mostly used in the design of high-speed and large-capacity storage device. Aiming at the shortcomings of serial port detection and data reading and writing methods, such as slow detection speed and long waiting time, a NAND Flash detection and control method based on USB2.0 bus was proposed. The communication and control circuit is designed by using FPGA logic control function and high-speed USB interface chip, and the command and operation control of Flash is realized by PC software. The user can complete the reading and writing, erasing detection and bad block calibration of NAND Flash through PC application program. The experimental results show that the method is fast, flexible, accurate and effective in reading, writing, erasing and bad block calibration, and can be widely used in the design and development of storage test devices.

Key words : USB bus；Flash memory；FPGA；detection