| VHDL編程系列之IEEE STANDARD VHDL | |
| 所屬分類：教程|講義 | |
| 上傳者：wenhuawu | |
| 文檔大小：1492 K | |
| 標(biāo)簽： 軟件 | |
| 所需積分：0分積分不夠怎么辦？ | |
| 文檔介紹：VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine read- able and human readable, it supports the development, verification, synthesis, and testing of hard- ware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the lan- guage and the advanced users of the language. | |
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