| 硬件加速器提升下一代SHARC數字信號處理器性能 | |
| 所屬分類：技術論文 | |
| 上傳者：chenyy | |
| 文檔大小：966 K | |
| 標簽： 微處理器|微控制器 | |
| 所需積分：0分積分不夠怎么辦？ | |
| 文檔介紹：The recently announced Analog Devices SHARC® ADSP-2146x processor incorporates hardware accelerators for implementing three widely used signal processing operations. The accelerators offload the core processor and have the potential to more than double the computational throughput of the processor. This paper introduces the accelerators using their application in next-generation audio systems as an example. | |
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